7/30/2023 0 Comments Primetime synopsys![]() ![]() ![]() Timing closure on DDR2 / DDR3 / PCIE interfaces. Low Power Design - Voltage Islands, Power Gating, Substrate - bias techniques. Interface with front - end ASIC teams to resolve issues. Provide technical guidance, mentoring to physical design engrs. ![]() He / She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate - bias. He / She should be able to do top - level floor planning, PG Planning, partitioning, placement, scan - chain - reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis / closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. BE / B.Tech / ME / M.Tech 3 years to 15 years. Physical Design Engineers Primary Responsibilities and Requirements. ![]()
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